1. Field of the Invention
The present invention relates to a metallization method and apparatus for manufacturing semiconductor devices. More particularly, the present invention relates to the selective metallization of apertures in insulative layers to form void-free intereconnections between conducting layers, including apertures such as contacts or vias in high aspect ratio sub-half micron applications, while preferably also forming a blanket layer on the insulative layer.
2. Background of the Related Art
Sub-half micron multilevel metallization is one of the key technologies for the next generation of very large scale integration (xe2x80x9cVLSIxe2x80x9d). The multilevel interconnections that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, lines or other features. Reliable formation of these interconnect features is very important to the success of VLSI and to the continued effort to increase circuit density and quality on individual substrates and die.
Two conventional methods for depositing Aluminum (Al) by chemical vapor deposition (xe2x80x9cCVDxe2x80x9d) include a blanket process ad a selective process. CVD processes typically involve the deposition of a film layer which occurs when a component of the chemical vapor contacts a xe2x80x9cnucleation sitexe2x80x9d on the substate. The component attaches to the nucleation site, creating a deposit surface on which ether deposition proceeds. A blanket CVD process typically deposits a film on the entire exposed surface of the substrate including the sidewall and bottom of appertures, as well as on the field because the entire substrate surface serves as a nucleation layer. A selective process typically deposits a film only on select nucleation surfaces provided on the substrate surface.
Blanket CVD metal deposition, such as CVD Al where a metal film is deposited on the entire exposed surface of the substrate, usually requires the presence of an electrically conductive nucleation layer. Thin metal films deposited during a blat CVD process an usually conformal and provide excellent step coverage, i.e., uniform thickness of layers on the sides and base of any aperture extending into the exposed surface of the substrate, even for very small aperture geometries. Therefore, CVD of aluminum is a common method used to fill aperture however, there are two primary difficulties associated with filling high aspect ratio (height to widthxe2x89xa72:1) apertures to form vias or contacts using blanket CVD methods. First, CVD films grow from all sides in a aperture and a void or key-hole may form in the filled aperture comprising the via or contact resulting in a compromised device. The formation of voids within these aperture is commonly referred to as crowning because the deposited layer grows upwardly and outwardly at the upper corners of the aperture and bridges at this location before the aperture has been completely filled. Second, the nucleation layer which must be deposited on the aperture walls to ensure deposition of the CVD layer thereon further reduces the width of the aperture, thereby increasing the difficulty of void-free filling of the aperture without voids.
Recent transmission electron microscopy data (xe2x80x9cTEMxe2x80x9d) reveal that voids exist in many interconnects formed by the CVD Al process even though standard electric tests of these interconnects do not evidence the existence of this void, Referring to FIG. 3, a TEM photograph shows a cross-sectional image of a 0.45 micron via filled with CVD Al. The image clearly indicates that voids exist in the metal layer deposited within the via structure. It should be recognized that this void is very difficult to detect by regular cross sectional standard electron microscopy (xe2x80x9cSEMxe2x80x9d) techniques, because some deformation occurs in soft aluminum during mechanical polishing of the slide preparation. In addition, electric conductivity tests many times do not detect structural abnormalities such as voids because the metal forms a bridging layer through at least a portion of the aperture. However, despite the generally positive electric conductivity test, conduction through a contact having a void therein may, over time, compromise the integrity of the integrated circuit devices in which the void is formed.
A TEM study of various CVD Al layers formed on substate indicates that the voids typically occur in a key hole pattern wherein the top portion of the via becomes sealed before the via has been entirely filled, i.e., crowning. Although a thin confound layer of CVD Al can typically be deposited in high aspect ratio apertures for creating contacts and vias at low temperatures, continued CVD deposition to completely fill the apertures typically results in the formation of voids therein. Extensive efforts have been focused on eliminating the voids in metal layers by modifying CVD processing steps and parameters.
Selective CVD Al deposition is based on the fact that the decomposition of the CVD Al precursor gas to provide a deposition film usually requires a source of electrons from a conductive nucleation film. In accordance with a conventional selective CVD Al deposition process, Al should grow in the bottom of an aperture where either a metal film or doped silicon from the underlying conductive layer has been exposed, but could not grow on the dielectric material on the field and forming the aperture walls. These underlying metal films and doped silicon, unlike the dielectric aperture walls, are both conductive and supply the electrons needed for decomposition of the Al prerursor gas and resulting deposition of Al. The result obtained through selective deposition is a xe2x80x9cbottom.upxe2x80x9d growth of CVD Al in the holes capable of filling very small dimension ( less than 0.25 xcexcm), high aspect ratio ( greater than 5:1) via or contact openings.
Referring to FIG. 2, a schematic diagram of an integrated circuit structure 10 shows a metal interconnect formed in via 14 flat was selectively nucleated by the conducting member 18 and grown uniformly upward towards the surface 20 of the dielectic layer 16. However, in actual practice of the selective deposition process, there are almost always defects on the surface of the dielectric and on the sidewalls of the apertures which provide free electrons and thus also serve as nucleation sites for CVD Al growth, causing unwanted nodule formation on the surface 20 and the walls of the apertures. Note that a nodule 12 was formed on the dielectric layer by loss of selectivity during a conventional selective CVD process to fill the via or contact 14. Various methods have been used to minimize the loss of selectivity that leads to nodule formation, especially in selective tungsten (W) technology. These methods have included, for example, preconditioning of the wafer surface and chemical mechanical polishing (CMP) of the surface to remove any nodules 12 which form on the wafer surface 20 during selective deposition. However, these methods complicate the processing steps required to form the desired circuit structure and significantly increase the expense of the integrated circuit manufacturing process. Likewise, some steps, such as CMP, cannot reach the sidewalls of the apertures. In addition, adding steps to the overall process increases the likelihood that defects may result in the formed structures.
Therefore, there remains a need for a metallizastion process for void-free filling of apertures, particularly high aspect ratio, sub-quarter micron wide apertures for forming contacts and vias. More particularly, it would be desirable to have a simple process requiring fewer processing steps to accomplish selective CVD Al deposition to create vias or contacts without nodule formation caused by the loss of selectivity on the field. It would also be desirable to have a single step process for both the selective CVD Al deposition in vias or contact and the blanket CVD Al deposition on the field.
The present invention provides a method and apparatus for forming an interconnect on a substrate having a dielectric layer covering at least a first conducting member, comprising the steps of forming a nucleation layer over the surface of the dielectric, etching an aperture through the nucleation layer and dielectric layer to form a floor exposing a portion of a conducting member and selectively depositing a metal by chemical vapor deposition on the interconnect floor and nucleation layer.
Another aspect of the invention provides a method and apparatus for preventing nodule formation on a first surface during selective chemical vapor deposition of metals on a second surface, the method comprising the steps of forming a nucleation layer on the first surface to provide substantially uniform growth of a deposited film.
Yet another aspect of the invention provides a method and apparatus for depositing metal films on select portions of a substrate, the method comprising the steps of providing at electrically conducting nucleation layer over select portions of the substrate and selectively depositing a metal film by chemical vapor deposition on the nucleation layer.